I design AI infrastructure for large language models: training systems, RL post-training pipelines, scheduling, offloading, and heterogeneous serving.
My systems work includes MuxRL for cluster-level RLVR service multiplexing, SpeedLoader for I/O-efficient distributed LLM operation, and SortedRL for efficient RL rollout scheduling.
I am a Data Science PhD candidate at the NUS HPC-AI Lab, advised by Dr. Yang You. My current research is MLSys and AI infrastructure: making LLM training, RLVR/post-training, inference, and serving efficient across clusters and heterogeneous memory/computation.
I usually work close to the systems boundary: algorithm-system co-design, runtime and scheduler design, data movement, model-state management, and performance debugging. Recent systems projects reflect this path: MuxRL on cluster-level RLVR multiplexing, SpeedLoader (NeurIPS 2024) on heterogeneous/offloaded LLM operation, and SortedRL on rollout scheduling for LLM RL.
Before moving into MLSys, I worked in neuroimaging and computational neuroscience. That earlier path still shapes how I think about noisy data, measurement, and complex systems.
Research focus:I worked on infrastructure for large-scale agentic post-training. My projects centered on cluster-level multiplexing for RLVR, service-oriented RL training, and unified model-state management, including MuxRL, Weaver, and the NexRL/Nex-N1 ecosystem.
The core systems theme was to turn post-training into an AI infrastructure problem: scheduling heterogeneous jobs, recycling idle GPUs across workloads, decoupling rollout/training/tool services, and hiding low-level parallelism details from algorithm designers.
I developed SortedRL, a system for online length-aware rollout scheduling in LLM reinforcement learning. It exploits output-length distribution during training to reduce rollout bubbles, construct efficient update batches, and maintain policy freshness.
The resulting scheduler reduced rollout scheduling bubbles by about 70% and cut the number of training steps for reasoning-model workloads by about 50%.
My PhD research focuses on systems for LLM training and inference under constrained accelerator memory. In the NeurIPS 2024 paper SpeedLoader, I redesigned data movement for offloaded and sharded LLM operation across heterogeneous hardware.
The broader goal is to make large-model infrastructure less bottlenecked by memory hierarchy, communication, and runtime scheduling overhead.
Manuscript under submission, 2026
ICML 2025 ES-FoMo III Workshop / arXiv 2026
NeurIPS 2024
IEEE Transactions on Medical Imaging
Frontiers in Neuroscience